CHIPOLY
Curator-TM
2.5/3D IC Thermal Analysis Challenges
- Thermal modeling has become a popular topic among designers of high-speed circuits and complex packaging. This has led to the adoption of better and more sophisticated thermal modeling tools and processes. The scales of chip, package, and system analysis vary—from nanometers to micrometers to centimeters—requiring a range of simulation techniques to cover these different scales.
- With the recent introduction of wafer-level front-end 3DIC chip stacking technologies, such as TSMC’s System-on-Integrated-Chips (SoIC), Chip-on-Wafer (CoW), or Wafer-on-Wafer (WoW) stacking, new design optimization techniques are needed for thermal considerations in the new generation of tightly packaged chiplets and cross-chip thermal coupling 3DICs.
- Mesh generation, for instance, is a fundamental component of multi-physics solutions. It is well known that using coarser meshes can speed up simulations but at the expense of accuracy. Large 3DIC designs, involving multiple chips, require repeated iterations of transient thermal analysis. Performing fine-grained transient thermal analysis on such large 3DIC designs using traditional CFD/FEA-based solvers is nearly impossible.
Curator™ Solution for System Thermal Simulation
Our DNN-based solver is designed to dramatically increase simulation speed by 100x, reducing the time required for chip thermal analysis and enabling faster design iterations, which will accelerate time-to-market for advanced chip designs.
The output temperature and power maps are being designed to be fully compatible with industry-standard thermal analysis software, facilitating seamless integration into existing workflows and enhancing the overall design process.
By modeling decay surfaces across multiple chips at different levels, our solution will support the most advanced IC architectures, including 2.5D and 3D ICs.